This invention relates to a plastic mold type semiconductor device.
FIG. 16 is a plan view of an example of the generally known prior plastic mold type semiconductor device. It is the lead frame for an SOJ (Small Outline J-Lead Package) type semiconductor device. FIG. 17 is a plan view showing the semiconductor elements of the lead frame of FIG. 16 . FIG. 18 is a sectional view showing section E-E' of FIG. 13.
In the center of this kind of lead frame is a die pad 2, and surrounding it are leads 3 for sending and receiving signals and voltage potential. The outer-frame will be omitted in the drawings of the lead frame below.
Bonding of the leads 3, as will be mentioned later, is done with wire; however to improve the characteristics of this bonding and also to improve the reliability of the connection, the lead ends 3a are plated with silver or gold. Also, in order to increase the current capacity, the lead end in the corner used for supplying power is made larger than the other lead ends.
In referring to FIG. 17 and FIG. 18, the semiconductor chip 1 is bonded to the top of the die pad 2 using die mount material 4. The bonding pads 9 of this semiconductor chip 1 are connected to the lead ends 3a with highly conductive thin metal wires 5 such as gold or aluminum. After wire bonding is completed, in order to protect the chip from the outside environment and to protect it from external forces and impact, a plastic mold 8 is formed around the entire chip. The portion of the leads that are covered with the plastic mold are called the inner-leads 6 and the portion of the leads outside of the plastic mold are called the outer-leads 7.
As shown in FIG. 18, the outer leads 7 are cut and separated from the outer-frame of the lead frame and then bent to form a J-shape.
In recent years, due to highly functional semiconductor devices, there is a tendency to increase the semiconductor chip size; however it becomes very difficult to place the enlarged semiconductor chip into a specified sized package.
For this reason, it is desired to reduce the size of the semiconductor chip itself; and so does the design rule itself.
However, in following this size reduced design rule, the wiring inside of the semiconductor chip must be made very thin, which increases the wire resistance. When the wire resistance increases, especially in the case of power supply or signal related wiring, external noise is picked up, making it easy for noise to be transmitted with the signal. Taking this into consideration, in trying to avoid the effects of noise it becomes difficult to increase the operating speed. Generally, power supply or signal related wiring takes up a large portion of the semiconductor chip area, and so the area of the wiring related to the power supply or signal must be reduced even though the above problems exist.
In order to do so, the following prior semiconductor devices have been proposed.
One of these is shown in FIG. 19, where the wiring capacity is increased by putting bonding pads, used to supply the potential, on top of the semiconductor chip 11 at both ends (20 and 21). In doing so, the wire resistance as well as the noise is reduced, thus making it possible to increase the operating speed.
However, in this semiconductor device, a new problem is created in that the wiring must be wired over a long distance. This is explained using the drawings.
In FIG. 19 and in FIG. 20 which is an illustrative drawing of FIG. 19, if the voltage potential or signal source (ground having 0 V potential) X is located in the upper left, the bonding pad 20 is very close to it and so connecting the bonding wire to the power supply or signal lead 30 is very simple to do; however because bonding pad 21 is so far away, it is necessary to run the wire halfway around the semiconductor chip 11. However, this is impossible in the construction of the device shown in FIG. 15.
In order to solve this problem, three-dimensional wiring is necessary. This is shown in FIG. 21 and FIG. 22 which is F-F' sectional view of FIG. 21.
In this construction, insulating adhesive 22 is used as the die mount material to bond the semiconductor chip 11 to the die pad 12. The potential supply or signal lead 31 is connected to a tie bar 32, and a bonding pad 23 is located on the die pad in the vicinity of another bonding pad 21 and the two are connected with a bonding wire 5. Also, a section of the die pad 12 is used as part of the wiring, and as shown in the section of FIG. 22 and the film diagram of FIG. 23, the wiring has become three-dimensional increasing the current supply or signal quantity.
However, in construction of this kind, because the semiconductor chip 11 and the die pad 12 are insulated by the insulating adhesive 22, it is necessary to control the thickness of the insulating adhesive. In other words, if the thickness of the insulating adhesive is very thin, there is the fear that the semiconductor chip 11 and the die pad 12 will directly short-circuited. Also if the film is thin, air voids exist and if moisture makes its way into one of these from outside, current leaks between the semiconductor chip 11 and the die pad 12 occur and the yield and reliability of the device are remarkably deteriorated. Therefore, it is necessary in order to maintain insulation, that the thickness of the thin film be a set thickness or more; however the manufacturing process for doing this is very complicated and difficult.